Search - uart VHDL

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] Uart

Description: 用ＦＰＧＡ，VHDL实现的Uart核，quartusII完整工程，实用-Using FPGA, VHDL realize the UART core, quartusII complete projects, practical
Platform: | Size: 631808 | Author: wanyou | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串行接口UART的用VHDL语言的简单实现，希望对大家有帮助-UART serial interface of the VHDL language with the simple realization, in the hope that everyone has to help
Platform: | Size: 3072 | Author: wangyd | Hits:

[VHDL-FPGA-Verilog] 8051core(vhdl)

Description: 再来一个8051的内核（VHDL语言），绝对好用，直接添加到QuartusII 中即可！！大家可以分享一下阿-Then a 8051 core (VHDL language), absolutely easy to use, directly added to the QuartusII it can! ! We can share the Arab-Israeli
Platform: | Size: 461824 | Author: 侯典华 | Hits:

[VHDL-FPGA-Verilog] UART

Description: VHDL实现UART通信,包括发送和接叫程序，使用方便-VHDL realize UART communications, including sending and then call the procedure, ease of use
Platform: | Size: 8192 | Author: fdf | Hits:

[VHDL-FPGA-Verilog] uart

Description: M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。-M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx
Platform: | Size: 18432 | Author: lc | Hits:

[Com Port] uart

Description: 一个基于硬件描述语言的uart核该软核灵巧方便，占用资源小波特率可调-A hardware description language based on the UART core of the soft-core smart convenient, small footprint adjustable baud rate
Platform: | Size: 3072 | Author: xu | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming
Platform: | Size: 5093376 | Author: 吕常智 | Hits:

[VHDL-FPGA-Verilog] uart_v11

Description: uart串口的vhdl语言程序。本人调试过，非常好用-serial UART VHDL Language Program. I debug, and very easy to use
Platform: | Size: 43008 | Author: hjj | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 在ＶＨＤＬ上编写了UART通信协议，对于ＦＰＧＡ开发有很大帮助-In VHDL on the preparation of a UART communication protocol, for FPGA development of great help
Platform: | Size: 143360 | Author: 王忠 | Hits:

[Other] u-uart

Description: UART verilog TX/RX OpenCores share
Platform: | Size: 5120 | Author: richman | Hits:

[Technology Management] VHDL-Handbook

Description: VHDL hand book for technical engineer or student for reference.
Platform: | Size: 1351680 | Author: David | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用VHDL实现的一个uart控制器，输入时钟为33M-Use VHDL to achieve a UART controller, input clock for the 33M
Platform: | Size: 1024 | Author: mu | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 基于FPGA的UART实现用VHDL编程-The UART-based FPGA using VHDL Programming
Platform: | Size: 524288 | Author: hyj1954 | Hits:

[VHDL-FPGA-Verilog] uart

Description: VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过-VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
Platform: | Size: 223232 | Author: 李特威 | Hits:

[Com Port] UART

Description: 使用方法： uart编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: uart programming, copied to the hard drive, open the project file with ISE can
Platform: | Size: 22528 | Author: yhz | Hits:

[VHDL-FPGA-Verilog] mini-uart

Description: Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
Platform: | Size: 253952 | Author: serein | Hits:

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[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] Uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] 8051core(vhdl)

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[Com Port] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart_v11

[VHDL-FPGA-Verilog] uart(Verilog)

[VHDL-FPGA-Verilog] UART

[Other] u-uart

[Technology Management] VHDL-Handbook

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[Com Port] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[Com Port] UART

[VHDL-FPGA-Verilog] mini-uart

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